Cascode Configuration Removes Miller Effect, Boosts PFC Performance

The power factor corrector (PFC) front end of an off-line power supply is subject to the operating frequency limitation caused by the Miller Effect of its associated power MOSFET. This effect is a property of any transistor configuration with a common source (MOSFET) or common emitter (bipolar transistor) configuration.

Most PFCs employ a boost converter based on a configuration with a common source MOSFET or common emitter power bipolar transistor.Figure 1 shows a conventional boost PFC kernel using a common source power MOSFET (Q). This is essentially a high gain amplifier that controls power by storing and releasing it into inductor L. During the MOSFET ON and OFF states, its drain voltage (V_DS) swings between almost zero and PFC output, which is generally 200V to 400V. This voltage periodically recharges the MOSFET's drain-to-source (C_DS) and drain-to-gate (C_DS) capacitances, and affects the gate-to-source (C_GS) capacitance (Fig. 2).

It's important to keep in mind that the V DS and drain-to-gate voltage (V_DG) are in counter-phase with respect to the V_GS and E_IN driving voltage. This means there is a negative feedback from the drain-to-gate, which is the Miller Effect¹ The Miller Effect increases the apparent input capacitance of a MOSFET or bipolar transistor.

To see the impact of the Miller Effect, consider how the boost transistor's input current depends on the Miller Effect and ignore the timing approach. The MOSFET's internal gate resistance (R_G) (Fig. 2, again) isn't essential and may be left out of the analysis.

Considering the MOSFET as an amplifier with negative feedback, notice that the following holds true if a small step input (E_IN) is applied to it:

dV_DG = dV_GS - dV_DS (1)

where V_DG = drain-to-gate voltage; V_GS = gate-to-source voltage, and V_DS = drain-to-source voltage.

Here, we are dealing with very small values, so they will be described by their differentials, but:

dV_DS = - dI_D × Z_L (2)

where dI_D = MOSFET drain current change and Z_L = load impedance .

Then:

dI_D = S × dV_GS (3)

where S = slope of the MOSFET's transconductance.

Substituting dI_D from Eq. 3 into Eq. 2 will obtain:

dV_DS = -S × Z_L × dV_GS (4)

Here, the expression for (S × Z_L) is the gain G of the amplifier built upon the MOSFET. The "minus" sign reflects the negative feedback. Thus,

G = S × Z_L (5)

With the assumption of Eq. 5, Eq. 4 is:

dV_DS = -G × dV_GS (6)

Substituting Eq. 6 into Eq. 1 for dV DS obtains:

dV_DG = dV_GS + G × dV_GS = dV_GS × (1 + G) (7)

The input current (I_IN) splits into two components, as shown in Figure 2:

I_GD = Current flowing from MOSFET gate-to-drain

I_GS = Current flowing from MOSFET gate-to-source:

I_IN = I_GD + I_GS (8)

The change of the gate-to-drain charge (Q_DG) causes current dI_GD so that:

I_GD = dQ_DG /dt (9)

Therefore,

I_GD = dQ_DG/dt = C_DG × dV_DG/dt (10)

or, assuming Eq. 7,

I_GD = dQ_DG/dt = C_DG × (1 + G) × dV_GS/dt (11)

And,

I_GS = C_GS × dV_GS/dt (12)

Consequently,

I_IN = C_DG × (1 + G) × dV_GS/dt + C _GS × dV_GS/dt

I_IN = [C_GS + C_DG × (1 + G) × dV_GS/dt (13)

where C_GS + C_DG × (1 + G) = C_APP is the apparent input capacitance of the MOSFET, which has to be recharged by the input current I IN . The value of the apparent capacitance C_APP can be very high and subsequently, the input current should have extremely high values, too.

Therefore,

I_IN = C_APP × dV_GS/dt (14)

For example, for the IXYS IXFR48N50Q MOSFET has the following characteristics along with circuit components:

C_GS = 7nF

C_DG = 0.230 nF

S = 30

Z_L = 230 Ω (PFC inductor inductance)

L = 300 µH ] @ 125 kHz operating frequency) and, therefore:

G = S × Z_L = 30 × 236 = 7000

And

C_APP = 0.230 × (1 + 7000) + 7 = 1.617 (µF)

It's clear that the input current must recharge this capacitance at the operating rate of, say, 15 V per 100 ns or 150 V /µs

And, from Equation 14, I_IN is 242.5 A.

Actually, C_DG and C_DS can vary by more than one order of magnitude or more when voltages V_GS and V_DS change (they reduce dramatically when these voltages rise from 0 to 40 V). The average I IN would not be that great, but instant values of about 10 to 20 A are possible. The MOSFET drivers can't produce this amount of current, which induces the well-known plateau on the MOSFET gate-drive characteristic (Fig. 3).²

So, the Miller Effect causes the apparent C_DG increase by a factor of a MOSFET amplifier gain, which can be on the order of a few thousand. This established negative feedback dramatically reduces the MOSFET's switching process, causing the above mentioned plateau in the gate-to-source signal timing diagram (Fig. 3, again). The Miller Effect limits the boost converter's (PFC) operating frequency to the values, which are far below the IC's and MOSFET's capabilities.

Zero voltage transition helps avoid the Miller Effect because the boost transistor drain-to-source voltage (V_DS) is controlled by an external resonant circuit^3,4 , not the MOSFET's gate signal (E_IN). This very reliable method requires another high-voltage MOSFET, a resonant inductor, two high-voltage diodes, and a handful of snubbing components, which suppress parasitic oscillations caused by the extra rectification diode as well as the inductor and its stray parameters. Power supplies operating above 800 W employ this type of PFC. Figure 4 shows waveforms of the gate drive and drain voltage.

For smaller power rates, a cascode configuration may be welcome. It's proven to be an easy and inexpensive solution. Because it's free of the Miller Effect, it helps to substantially increase the PFC operating frequency.

A very good example of a cascode schematic arrangement is described in an article authored by Scot Lester.⁵ This paper discusses the input and output voltage increase in the cascode configuration. However, it leaves out a more important ability of a cascode scheme—getting rid of the Miller Effect to enable operation at higher frequencies.

Figure 5 depicts a cascode amplifier employing boost controller U1 (Texas Instruments' UC3854A may be a good implementation), driving a low-voltage and low- R_DS MOSFET (Q1) through resistor R. This common source configuration has a very-low-impedance drain load because high-voltage transistor Q2 is a common-gate configuration (Fig. 6), and Q1 "sees" its source. In operation, the Q1 drain voltage swing is only about V_CC, while the load is a very low impedance. This doesn't trigger the Miller Effect due to a very low voltage gain of Q1. The upper high-voltage MOSFET Q2 has a common gate connection, which eliminates the negative feedback and thus the Miller Effect. This is why the apparent capacitance of Q2 is just the gate-to-source capacitance (and even less due to the positive feedback through Q2, C_DS).

During operation, both Q1 and Q2 are either ON or OFF. When the Q2 drain voltage changes rapidly, it affects the gate and source networks through capacitances C_DG and C_DS. Diode D serves as a clamp for the Q2 source, connecting it to the V_CC when Q2 turns off and its drain pulls up the source through the C_DS. It's worth mentioning that the Q2 drain seriously affects the Q2 gate circuit, which tends to change the V_CC. To prevent this, the source of the V_CC should be able to resist both pull-up and pull-down changes, providing substantial sinking and sourcing currents. The V_CC source can be made upon a linear voltage regulator LM78L15 and an operational amplifier, capable of producing output current of around 1 A. ON Semiconductor's TCA0372 may be a good choice for this step.

Figures 7 and 8 show a cascode configuration. The waveforms have no evidence of the Miller Effect. The cascode solution can be used at frequencies far above those being operated at by conventional PFCs.